// *********************************************************************************
// Project Name : zkx2024
// Author       : Glqu
// Email        : QGL_MAX@163.com
// Create Time  : 2024-04-13
// File Name    : testbench.v
// Module Name  :
// Called By    :glqu
// Abstract     :
//
// 
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2024-04-13    Macro           1.0                     Original
//  
// *********************************************************************************

`timescale 1ns/1ps
module testbench();
logic   [0:0]   CLK;
logic   [0:0]   RST_N;
logic   [31:0]  I_DATA;
logic   [3:0]   CRC_OUT;
logic   [0:0]   OUT_VLD;
always #2 CLK = ~CLK;

//----------------------------------
//gen fsdb
//----------------------------------

initial begin
    $fsdbDumpfile("tb_crc.fsdb");
    $fsdbDumpvars;
end

initial begin
    CLK=0;
    RST_N=1;
    #5
    RST_N=0;
    #2
    RST_N=1;
    #2
    I_DATA=32'h369abccc;
    #4
    I_DATA=32'h369abcde;
    #4
    I_DATA=32'h36911111;
    #5
    I_DATA=32'h23456789;
    #7
    I_DATA=32'h01234567;

    #500;
    $finish;
end

//inst_dut

en_crc#(.DATA_WIDTH(32),
        .CRC_WIDTH(4))
        dut(.*);
/*
(
    .CLK(CLK),
    .RST_N(RST_N),
    .I_DATA_EN(I_DATA_EN),
    .I_DATA(I_DATA),
    .DATA_OUT(DATA_OUT),
    .OUT_VLD(OUT_VLD)
    );
*/
endmodule


